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Cypress Semiconductor /psoc63 /SRSS /CLK_ROOT_SELECT[1]

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Interpret as CLK_ROOT_SELECT[1]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PATH0)ROOT_MUX 0 (NO_DIV)ROOT_DIV 0 (ENABLE)ENABLE

ROOT_DIV=NO_DIV, ROOT_MUX=PATH0

Description

Clock Root Select Register

Fields

ROOT_MUX

Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.

0 (PATH0): Select PATH0 (can be configured for FLL)

1 (PATH1): Select PATH1 (can be configured for PLL0, if available in the product)

2 (PATH2): Select PATH2 (can be configured for PLL1, if available in the product)

3 (PATH3): Select PATH3 (can be configured for PLL2, if available in the product)

4 (PATH4): Select PATH4 (can be configured for PLL3, if available in the product)

5 (PATH5): Select PATH5 (can be configured for PLL4, if available in the product)

6 (PATH6): Select PATH6 (can be configured for PLL5, if available in the product)

7 (PATH7): Select PATH7 (can be configured for PLL6, if available in the product)

8 (PATH8): Select PATH8 (can be configured for PLL7, if available in the product)

9 (PATH9): Select PATH9 (can be configured for PLL8, if available in the product)

10 (PATH10): Select PATH10 (can be configured for PLL9, if available in the product)

11 (PATH11): Select PATH11 (can be configured for PLL10, if available in the product)

12 (PATH12): Select PATH12 (can be configured for PLL11, if available in the product)

13 (PATH13): Select PATH13 (can be configured for PLL12, if available in the product)

14 (PATH14): Select PATH14 (can be configured for PLL13, if available in the product)

15 (PATH15): Select PATH15 (can be configured for PLL14, if available in the product)
ROOT_DIV

Selects predivider value for this clock root and DSI input.

0 (NO_DIV): Transparent mode, feed through selected clock source w/o dividing.

1 (DIV_BY_2): Divide selected clock source by 2

2 (DIV_BY_4): Divide selected clock source by 4

3 (DIV_BY_8): Divide selected clock source by 8
ENABLE

Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data